1. Field of the Invention
The present invention relates to a semiconductor device having an element isolation structure by an STI (Shallow Trench Isolation) method, and also to a manufacturing method of the semiconductor device.
2. Description of the Related Art
Conventionally, element isolation structures by STI methods, in each of which a trench formed in an element isolation region is filled with an insulating material to ensure electrical insulation between active regions, (hereinafter simply referred to as STI element isolation structures), are used as element isolation structures of semiconductor devices. The STI element isolation structures are expected to meet recent requirement of further reduction in scale of semiconductor elements because such STI element isolation structures can make sure element isolation with no protrusion from the surface of the substrate, such as a field oxidation film by a so-called LOCOS method.
(Patent Document 1)
Japanese Patent Application Laid-open No. 2003-203989
In an element isolation structure as represented by an STI element isolation structure, an insulating material for element isolation applies a compressive stress to a neighboring element region. That is, although silicon oxide having its dielectric constant of 3.9 is normally used as the insulating material for an STI element isolation structure so as to avoid an increase in parasitic capacitance, the silicon oxide applies a compressive stress to a neighboring active region because the silicon oxide is made with volume expansion relatively to the original silicon. Under the influence of such a compressive stress, variation in element characteristics by size appears remarkably. When the compressive stress increases to exceed the elastic limit of the parent crystal of the semiconductor substrate, dislocation, stacking fault, or the like, is generated and it brings about, for example, PN-junction leak. The influence of such a compressive stress is more remarkable as the element size is reduced. Therefore, making the compressive stress the minimum brings about an improvement of yield of semiconductor elements and it contributes further scale-down of a semiconductor element.
Further, it has been found by recent study that the influence of a compressive stress upon an active region by an STI element isolation structure varies between a first conductivity type element, for example, a first conductivity type (N type) MOS transistor (NMOS transistor), and a second conductivity type element, for example, a second conductivity type (P type) MOS transistor (PMOS transistor). That is, in the case of an NMOS transistor, either of a compressive stress in a direction parallel to the length of the channel to an active region (in a channel length direction), and a compressive stress in a direction parallel to the width of the channel (in a channel width direction), causes a decrease in operation current. Contrastingly, in the case of a PMOS transistor, only a compressive stress in a channel width direction to an active region causes a decrease in operation current, and a compressive stress in a channel length direction contributes an improvement of the operation current.
In the case that a trench formed in an element isolation region is filled with an insulating material to make an STI element isolation structure, compressive stresses applied from the STI element isolation structure to active regions are inevitably isotropic. Therefore, when such an STI element isolation structure is used for a CMOS transistor in which N-type and P-type MOS transistors are formed on the same semiconductor substrate, it is difficult to improve both the operation currents of the N-type and P-type MOS transistors.
On this point, as a method for avoiding a decrease in operation current, a technique has been devised in which the intervals between neighboring active regions (that is, the width of each STI element isolation structure) are varied between a channel length direction and a channel width direction, for example, as disclosed in JP-A-2003-203989. Even in this case, however, because compressive stresses applied from the STI element isolation structure to active regions are isotropic, control of the compressive stresses is insufficient, and it is difficult to cope with a CMOS transistor as described above.
On the other hand, a trial is made in which each channel region is formed in a direction equivalent to (100). By this technique, each channel region is in a state of having been rotated by 45° from its ordinary position, and the quantity of strain (the quantity of stress tensor) when a stress in a direction along the channel region is applied to an active region is remarkably decreased. Thus, the strain due to the stress from oxide is held down and the above quantity of stress tensor is decreased. On the other hand, however, it is difficult to positively give an active region a strain of a desired intensity in a desired direction so as to improve the operation current in the active region, and it is not expected to considerably improve characteristics by introducing a strain into an active region.
On the other hand, a technique has been devised in which an insulating film for buffering a compressive stress (a liner nitride film) is interposed between silicon and silicon oxide in an STI element isolation structure. However, even when such a liner nitride film is provided, there still remains pressure on an STI side wall by the silicon oxide of the STI element isolation structure, and it is difficult to reduce the pressure. In this case, a method is also known in which the thickness of the liner nitride film is controlled to be equivalent to the thickness of the silicon oxide. However, there is a large influence upon an increase in parasitic capacitance by the STI element isolation structure.